Synchronous memory interface with test code input

ABSTRACT

A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals provided on the address input connections and not the data input/output connections. The test mode can be entered using either commands or a combination of commands and an electronic key.

RELATED APPLICATION

This is a divisional application of U.S. patent application Ser. No.11/006,328, filed Dec. 6,2004, titled “SYNCHRONOUS FLASH MEMORY WITHTEST CODE INPUT”, which is a continuation application of U.S. patentapplication Ser. No. 09/829,136, filed Apr. 9, 2001, titled “SYNCHRONOUSFLASH MEMORY WITH TEST CODE INPUT” (now U.S. Pat. No. 6,865,702, issuedMar. 8, 2005), which is commonly assigned, the entire contents of whichare incorporated herein by reference

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to non-volatile memory devicesand in particular the present invention relates to testing non-volatilememory.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types ofmemory. One type is RAM (random-access memory). This is typically usedas main memory in a computer environment. RAM refers to read and writememory; that is, you can both write data into RAM and read data fromRAM. This is in contrast to ROM, which permits you only to read data.Most RAM is volatile, which means that it requires a steady flow ofelectricity to maintain its contents. As soon as the power is turnedoff, whatever data was in RAM is lost.

Computers almost always contain a small amount of read-only memory (ROM)that holds instructions for starting up the computer. Unlike RAM, ROMcannot be written to. An EEPROM (electrically erasable programmableread-only memory) is a special type non-volatile ROM that can be erasedby exposing it to an electrical charge. Like other types of ROM, EEPROMis traditionally not as fast as RAM. EEPROM comprise a large number ofmemory cells having electrically isolated gates (floating gates). Datais stored in the memory cells in the form of charge on the floatinggates. Charge is transported to or removed from the floating gates byprogramming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flashmemory is a type of EEPROM that can be erased and reprogrammed in blocksinstead of one byte at a time. Many modern PCS have their BIOS stored ona flash memory chip so that it can easily be updated if necessary. Sucha BIOS is sometimes called a flash BIOS. Flash memory is also popular inmodems because it enables the modem manufacturer to support newprotocols as they become standardized.

A typical Flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed in a random basis bycharging the floating gate. The charge can be removed from the floatinggate by a block erase operation. The data in a cell is determined by thepresence or absence of the charge in the floating gate.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higherclock speeds than conventional DRAM memory. SDRAM synchronizes itselfwith a CPU's bus and is capable of running at 100 MHZ, about three timesfaster than conventional FPM (Fast Page Mode) RAM, and about twice asfast EDO (Extended Data Output) DRAM and BEDO (Burst Extended DataOutput) DRAM. SDRAM's can be accessed quickly, but are volatile. Manycomputer systems are designed to operate using SDRAM, but would benefitfrom non-volatile memory.

Further, as the geometries and cost of integrated circuit memoriescontinues to be reduced, the costs associated with testing the memoriesis becoming a more significant component of the total manufacturingcost. Specifically, before delivery to end users, each memory chip mustbe tested to ensure that it is functioning properly. Typically, theentire memory array must be tested.

For example, a common testing procedure for a memory connected to amemory tester is to first have the tester send a command to the memoryto erase all of its bits to “1”. The tester then reads the memory cellsto verify that they are all “1”. Next, zeros are written to all of thebits of the memory and the cells are read in order to verify that theyare all “0”. Then, all of the bits of the memory are erased, acheckerboard pattern is written to the memory and the cells are read inorder to verify that the checkerboard pattern is present. Finally, allof the bits of the memory are erased, an inverted checkerboard patternis written to the memory, and the cells are read in order to verify thatthe inverted checkerboard pattern is present. This testing procedure isa good way to find out if any of the bits of the memory are shorted toan adjacent bit, to a high level, or to a low state, or if there are anyother problems.

Because the cost of testing has becoming a significant component of thetotal manufacturing cost of memory chips, testing using compressed datalines can be implemented. See U.S. Pat. No. 5,787,097 entitled “OutputData Compression Scheme for Use in Testing IC Memories,” issued Jul. 28,1998. This patent describes a system for compressing data during a testoperation so that multiple memory devices can be simultaneously testedusing a common tester. That is, each memory device uses a subset of itsdata output connections.

To conduct test operations on a memory device, the memory device isplaced in a test mode. Because the test mode should not be enteredaccidentally, an electronic key is often used to restrict access to testmodes. For example, a high voltage may be required on a specific inputconnection to enter a test mode. Further, a test mode code can beprovided on data input connections to instruct the memory device whichtest is to be selected. If the memory is operated in a compressed mode,complicated circuitry is needed to detect the test mode codes on thedata connections.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora non-volatile memory device that can operate in a compressed data modeand easily select between different test modes.

SUMMARY OF THE INVENTION

The above-mentioned problems with memory devices and other problems areaddressed by the present invention and will be understood by reading andstudying the following specification.

In one embodiment, a non-volatile memory device comprises address inputconnections to receive externally provided signals, and controlcircuitry coupled to the address input connections to place thenon-volatile memory device in a test mode selected by the externallyprovided signals.

In another embodiment, a flash memory device comprises an array ofnon-volatile memory cells, control input connections to receive controlsignals, data connections for bi-directional data communication, addressinput connections to receive externally provided address and test modecode signals, and control circuitry coupled to the address inputconnections to place the non-volatile memory device in a test modeselected by the test mode code signals.

A memory system is provided that comprises an external memorycontroller, and a flash memory device coupled to the external memorycontroller. The flash memory device comprises an array of non-volatilememory cells, control input connections to receive control signals fromthe external memory controller, data connections for bi-directional datacommunication with the external memory controller, address inputconnections to receive externally provided address and test mode codesignals from the external memory controller, and control circuitrycoupled to the address input connections to place the non-volatilememory device in a test mode selected by the test mode code signals.

A method of testing a non-volatile memory device comprises initiating atest operation of the non-volatile memory device, and selecting a testmode in response to a test code provided on address inputs.

In another embodiment, a method of testing a non-volatile memory devicecomprises checking a state of a test latch circuit, receiving test modecommands on address inputs, placing the non-volatile memory device in atest mode if the test latch circuit is in a first state, and prohibitingthe test mode if the test latch circuit is in a second state. A testmode is selected in response to a test code provided on the addressinputs.

In yet another embodiment, a method of operating a non-volatile memorydevice comprises performing a first Load Command Register operation.Wherein the first Load Command Register operation comprises receiving atest mode command on address input connections when a chip select inputis active, a row access strobe input is active, a column access strobeinput is active and a write enable input is inactive. The test modecommand initiates a test mode. The method further comprises performing asecond Load Command Register operation. Wherein the second Load CommandRegister operation comprises receiving a test code command on addressinput connections when a chip select input is active, a row accessstrobe input is active, a column access strobe input is active and awrite enable input is inactive. The test code command instructs thememory device to perform a selected test operation.

A method of testing a memory device having X selectable tests isprovided. The method comprises initiating a test mode, and selecting oneof the X selectable tests using a test code provided on address inputconnections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a synchronous flash memory of the presentinvention;

FIG. 2 illustrates an interconnect pin assignment of one embodiment ofthe present invention; and

FIG. 3 is a timing diagram of an example operation of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of present embodiments, referenceis made to the accompanying drawings that form a part hereof, and inwhich is shown by way of illustration specific embodiments in which theinventions may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that logical, mechanical and electrical changes may be madewithout departing from the spirit and scope of the present invention.The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the claims.

Referring to FIG. 1, a block diagram of one embodiment of the presentinvention is described. The memory device 100 includes an array ofnon-volatile flash memory cells 102. The array is arranged in aplurality of addressable banks. In one embodiment, the memory containsfour memory banks 104, 106, 108 and 110. Each memory bank containsaddressable sectors of memory cells. The data stored in the memory canbe accessed using externally provided location addresses received byaddress register 112 via address signal connections. The addresses aredecoded using row address multiplexer circuitry 114. The addresses arealso decoded using bank control logic 116 and row address latch anddecode circuitry 118. To access an appropriate column of the memory,column address counter and latch circuitry 120 couples the receivedaddresses to column decode circuitry 122. Circuit 124 providesinput/output gating, data mask logic, read data latch circuitry andwrite driver circuitry. Data is input through data input registers 126and output through data output registers 128 via data connections.Command execution logic 130 is provided to control the basic operationsof the memory device. A state machine 132 is also provided to controlspecific operations performed on the memory array and cells. A statusregister 134 and an identification register 136 can also be provided tooutput data. The command circuit 130 and/or state machine 132 can begenerally referred to as control circuitry to control read, write, eraseand other memory operations. The data connections are typically used forbi-directional data communication. The memory can be coupled to anexternal processor 200 for operation or testing.

FIG. 2 illustrates an interconnect pin assignment of one embodiment ofthe present invention. The memory package 150 has 54 interconnect pins.The pin configuration is substantially similar to available SDRAMpackages. Two interconnects specific to the present invention are RP#152 and Vccp 154. Although the present invention may share interconnectlabels that are appear the same as SDRAM's, the function of the signalsprovided on the interconnects are described herein and should not beequated to SDRAM's unless set forth herein.

Prior to describing the operational features of the memory device, amore detailed description of the interconnect pins and their respectivesignals is provided. The input clock connection is used to provide aclock signal (CLK). A system clock can drive the clock signal, and allsynchronous flash memory input signals are sampled on the positive edgeof CLK. CLK also increments an internal burst counter and controls theoutput registers.

The input clock enable (CKE) connection is used to activate (HIGH state)and deactivates (LOW state) the CLK signal input. Deactivating the clockinput provides POWER-DOWN and STANDBY operation (where all memory banksare idle), ACTIVE POWER-DOWN (a memory row is ACTIVE in either bank) orCLOCK SUSPEND operation (burst/access in progress). CKE is synchronousexcept after the device enters power-down modes, where CKE becomesasynchronous until after exiting the same mode. The input buffers,including CLK, are disabled during power-down modes to provide lowstandby power. CKE may be tied HIGH in systems where power-down modes(other than RP# deep power-down) are not required.

The chip select (CS#) input connection provides a signal to enable(registered LOW) and disable (registered HIGH) a command decoderprovided in the command execution logic. All commands are masked whenCS# is registered HIGH. Further, CS# provides for external bankselection on systems with multiple banks, and CS# can be considered partof the command code; but may not be necessary.

The input command input connections for RAS#, CAS#, and WE# (along withCAS#, CS#) define a command that is to be executed by the memory. Theinput/output mask (DQM) connections are used to provide input masksignals for write accesses and an output enable signal for readaccesses. Input data is masked when DQM is sampled HIGH during a WRITEcycle. The output buffers are placed in a high impedance (High-Z) state(after a two-clock latency) when DQM is sampled HIGH during a READcycle. DQML corresponds to data connections DQ0-DQ7 and DQMH correspondsto data connections DQ8-DQ15. DQML and DQMH are considered to be thesame state when referenced as DQM.

Address inputs 133 are primarily used to provide address signals. In theillustrated embodiment the memory has 12 lines (A0-A11). Other signalscan be provided on the address connections, as described below. In oneembodiment of the present invention, test mode codes are received by thememory via the address inputs. The address inputs are sampled during anACTIVE command (row-address A0-A11) and a READ/WRITE command(column-address A0-A7) to select one location in a respective memorybank. The address inputs are also used to provide an operating code(OpCode) during a LOAD COMMAND REGISTER operation, explained below.Address lines A0-A11 are also used to input mode settings during a LOADMODE REGISTER operation.

An input reset/power-down (RP#) connection 140 is used for reset andpower-down operations. Upon initial device power-up, a 100 μs delayafter RP# has transitioned from LOW to HIGH is required in oneembodiment for internal device initialization, prior to issuing anexecutable command. The RP# signal clears the status register, sets theinternal state machine (ISM) 132 to an array read mode, and places thedevice in a deep power-down mode when LOW. During power down, all inputconnections, including CS# 142, are “Don't Care” and all outputs areplaced in a High-Z state. When the RP# signal is equal to a VHH voltage(5V), all protection modes are ignored during WRITE and ERASE. The RP#signal also allows a device protect bit to be set to 1 (protected) andallows block protect bits of a 16 bit register, at locations 0 and 15 tobe set to 0 (unprotected) when brought to VHH. The protect bits aredescribed in more detail below. RP# is held HIGH during all other modesof operation.

Bank address input connections, BA0 and BA1 define which bank an ACTIVE,READ, WRITE, or BLOCK PROTECT command is being applied. The DQ0-DQ15connections 143 are data bus connections used for bi-directional datacommunication. A VCCQ connection is used to provide isolated power tothe DQ connections to improved noise immunity. In one embodiment,VCCQ=Vcc or 1.8V±0.15V. The VSSQ connection is used to isolated groundto DQs for improved noise immunity. The VCC connection provides a powersupply, such as 3V. A ground connection is provided through the Vssconnection. Another optional voltage is provided on the VCCP connection144. The VCCP connection can be tied externally to VCC, and sourcescurrent during device initialization, WRITE and ERASE operations. Thatis, writing or erasing to the memory device can be performed using aVCCP voltage, while all other operations can be performed with a VCCvoltage. The Vccp connection is coupled to a high voltage switch/pumpcircuit 145.

The following sections provide a more detailed description of theoperation of the synchronous flash memory. One embodiment of the presentinvention is a nonvolatile, electrically sector-erasable (Flash),programmable read-only memory containing 67,108,864 bits organized as4,194,304 words by 16 bits. Other population densities are contemplated,and the present invention is not limited to the example density. Eachmemory bank is organized into four independently erasable blocks (16total). To ensure that critical firmware is protected from accidentalerasure or overwrite, the memory can include sixteen 256K-word hardwareand software lockable blocks. The memory's four-bank architecturesupports true concurrent operations.

A read access to any bank can occur simultaneously with a backgroundWRITE or ERASE operation to any other bank. The synchronous flash memoryhas a synchronous interface (all signals are registered on the positiveedge of the clock signal, CLK). Read accesses to the memory can be burstoriented. That is, memory accesses start at a selected location andcontinue for a programmed number of locations in a programmed sequence.Read accesses begin with the registration of an ACTIVE command, followedby a READ command. The address bits registered coincident with theACTIVE command are used to select the bank and row to be accessed. Theaddress bits registered coincident with the READ command are used toselect the starting column location and bank for the burst access.

The synchronous flash memory provides for programmable read burstlengths of 1, 2, 4 or 8 locations, or the full page, with a burstterminate option. Further, the synchronous flash memory uses an internalpipelined architecture to achieve high-speed operation. In general, thesynchronous flash memory is configured similar to a multi-bank DRAM thatoperates at low voltage and includes a synchronous interface. Each ofthe banks is organized into rows and columns.

The synchronous flash is powered up and initialized in a predefinedmanner. After power is applied to VCC, VCCQ and VCCP (simultaneously),and the clock signal is stable, RP# 140 is brought from a LOW state to aHIGH state. A delay, such as a 100 μs delay, is needed after RP#transitions HIGH in order to complete internal device initialization.After the delay time has passed, the memory is placed in an array readmode and is ready for Mode Register programming or an executablecommand. After initial programming of a non-volatile mode register 147(NVMode Register), the contents are automatically loaded into a volatileMode Register 148 during the initialization. The device will power up ina programmed state and will not require reloading of the non-volatilemode register 147 prior to issuing operational commands.

The Mode Register 148 is used to define the specific mode of operationof the synchronous flash memory. This definition includes the selectionof a burst length, a burst type, a CAS latency, and an operating mode.The Mode Register is programmed via a LOAD MODE REGISTER command andretains stored information until it is reprogrammed. The following tabledefines the Load Mode Register command. CS RAS CAS WE NAME (FUNCTION) ## # # ADDR DQs LOAD COMMAND L L L H Command X REGISTER Code

The contents of the Mode Register may be copied into the NVMode Register147. The NVMode Register settings automatically load the Mode Register148 during initialization. Those skilled in the art will recognize thatan SDRAM requires that a mode register must be externally loaded duringeach initialization operation. The present memory allows a default modeto be stored in the NV mode register 147. The contents of the NV moderegister are then copied into a volatile mode register 148 for accessduring memory operations.

Mode Register bits M0-M2 specify a burst length, M3 specifies a bursttype (sequential or interleaved), M4-M6 specify a CAS latency, M7 and M8specify a operating mode.

Read accesses to the synchronous flash memory can be burst oriented,with the burst length being programmable. The burst length determinesthe maximum number of column locations that can be automaticallyaccessed for a given READ command. When a READ command is issued, ablock of columns equal to the burst length is effectively selected. Theblock is uniquely selected by address lines A1-A7 when the burst lengthis set to two, by A2-A7 when the burst length is set to four, and byA3-A7 when the burst length is set to eight. The remaining (leastsignificant) address bit(s) are used to select the starting locationwithin the block. Accesses within a given burst may be programmed to beeither sequential or interleaved. This is referred to as the burst typeand is selected via bit M3. The ordering of accesses within a burst isdetermined by the burst length, the burst type and the starting columnaddress.

A test mode must be entered to initiate a test operation on the memorydevice. During production testing, a software command can be used toenter the test mode. That is, providing a specific command sequence tothe memory can enter the test mode. To prevent a user from accidentallyinitiating a test mode operation, a non-volatile data register 180 isprovided. If the data register is not programmed, a test mode can beentered using commands only. Once the data register is programmed, oftenfollowing production testing, an electronic key is required to initiatea test mode. For example, an elevated voltage must be provided on apre-selected address input connection to initiate a test mode. Thus, avoltage detection circuit 190 monitors the address input. Once anelevated voltage is detected, the test mode is entered and a selectedtest can be specified.

As explained above, the memory can be operated in a compressed mode suchthat only a portion of its data (DQ) connections are used. For example,in one embodiment a four-to-one compression scheme uses four of sixteendata connections. Four memory devices can be tested using onesixteen-wide data bus. If the data lines are used to communicate testcodes, congestion can be experienced which results in bus wait time. Toover come this problem, the present invention uses some of the addresslines to provide the test mode codes.

In one embodiment, providing a command sequence that includes threesequential Load Command Register operations enters a test command mode.A Load Command Register operation is described in the following table.CS RAS CAS WE NAME (FUNCTION) # # # # ADDR DQs LOAD COMMAND L L L HCommand/ X REGISTER Code

Referring to FIG. 3, a simplified timing diagram is provided of a sampletest operation. At times T0 and T1, first and second Load CommandRegister operations are accompanied by address signals, code 1 and code2, which instruct the memory to enter a test mode. The third LoadCommand Register operation, at time T2, is accompanied by a test commandcode provided on the address inputs that instruct the memory which testmode operation is to be performed.

CONCLUSION

A synchronous non-volatile memory device has been described that hasaddress input connections and data input/output connections. A testoperation can be initiated that use signals provided on the addressinput connections and not the data input/output connections. The testmode can be entered using either commands or a combination of commandsand an electronic key.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. A synchronous memory interface, comprising: address input connectionsto receive externally provided signals; and wherein the synchronousmemory interface is adapted to select a test mode of operation selectedby the externally provided signals on the address input connections. 2.The synchronous memory interface of claim 1, further comprising a testmode latch circuit.
 3. The synchronous memory interface of claim 2,wherein the synchronous memory interface is adapted to initiate a testoperation in response to externally provided commands when the test modelatch is in a first state.
 4. The synchronous memory interface of claim2, wherein the synchronous memory interface is adapted to initiate atest operation in response to externally provided commands and anelectronic key when the test mode latch is in a second state.
 5. Thesynchronous memory interface of claim 4, wherein the electronic keycomprises a voltage detection circuit coupled to an external inputconnection to detect a selected voltage level applied to the externalinput connection.
 6. A synchronous memory interface, comprising: controlinput connections to receive control signals; data connections forbi-directional data communication; address input connections to receiveexternally provided address and test mode code signals; and controlcircuitry coupled to the address input connections adapted to place thesynchronous memory interface and a coupled memory device in a test modeselected by the test mode code signals.
 7. The synchronous memoryinterface of claim 6, further comprising a test mode latch circuit. 8.The synchronous memory interface of claim 7, wherein the controlcircuitry initiates a test operation in response to externally providedcommands when the test mode latch is in a first state.
 9. Thesynchronous memory interface of claim 7, wherein the control circuitryinitiates a test operation in response to externally provided commandsand an electronic key circuit when the test mode latch is in a secondstate.
 10. The synchronous memory interface of claim 9, wherein theelectronic key circuit comprises a voltage detection circuit coupled toan external input connection of the memory interface to detect anelevated voltage applied to the external input connection.
 11. Thesynchronous memory interface of claim 10, wherein the external inputconnection is one of the address input connections.
 12. A synchronousnon-volatile memory interface, comprising: control input connections toreceive control signals; data connections for bi-directional datacommunication; address input connections to receive externally providedaddress and test mode code signals; and wherein the synchronousnon-volatile memory interface is adapted to perform a first and secondLoad Command Register operation, where the first Load Command Registeroperation comprises receiving a test mode command to initiate a testmode on address input connections when a chip select input is active, arow access strobe input is active, a column access strobe input isactive and a write enable input is inactive, and where the second LoadCommand Register operation comprises receiving a test code command onaddress input connections to instruct the synchronous non-volatilememory interface to perform a selected test operation when a chip selectinput is active, a row access strobe input is active, a column accessstrobe input is active and a write enable input is inactive.
 13. Thesynchronous non-volatile memory interface of claim 12, wherein thesynchronous non-volatile memory interface is adapted to check a state ofa test latch circuit and place the synchronous non-volatile memoryinterface in the test mode if the test latch circuit is in a firststate, and prohibit the synchronous non-volatile memory interface fromentering the test mode if the test latch circuit is in a second state.14. The synchronous non-volatile memory interface of claim 13, whereinthe synchronous non-volatile memory interface is adapted to place thesynchronous non-volatile memory interface in the test mode if the testlatch circuit is in the second state, and a high voltage signal isdetected on a pre-determined address input.
 15. A synchronous memoryinterface, comprising: control input connections to receive controlsignals; data connections for bi-directional data communication; addressinput connections to receive externally provided address and test modecode signals; and wherein the synchronous memory interface is adapted toreceive test mode commands on the address inputs, check a state of anon-volatile test latch circuit, place the synchronous memory interfacein a test mode if the test latch circuit is in a first state, andprohibit the synchronous memory interface from entering the test mode ifthe test latch circuit is in a second state.
 16. The synchronous memoryinterface of claim 15, wherein the synchronous memory interface isadapted to place the synchronous memory interface in the test mode ifthe test latch circuit is in the second state, and a high voltage signalis detected on a pre-determined address input.
 17. The synchronousmemory interface of claim 15, wherein the synchronous memory interfaceis adapted to select a test mode in response to a test code provided onthe address inputs.
 18. A synchronous memory interface, comprising:control input connections to receive control signals; a first number ofdata connections for bi-directional data communication; address inputconnections to receive externally provided address and command signals;and control circuitry to place the synchronous memory interface in acompressed data mode such that the first number of bits of data arecommunicated using a second number of data connections, wherein thesecond number of data connections is less than or equal to the firstnumber, and where the control circuitry is coupled to the address inputconnections to place the synchronous memory interface and a couplednon-volatile memory device in a test mode selected by test mode codesignals.
 19. The synchronous memory interface of claim 18, furthercomprising a test mode latch circuit, and the control circuitryinitiates a test operation in response to externally provided commandswhen the test mode latch is in a first state.
 20. The synchronous memoryinterface of claim 18, further comprising a test mode latch circuit, andthe control circuitry initiates a test operation in response toexternally provided commands and an electronic key circuit when the testmode latch is in a second state.
 21. The synchronous memory interface ofclaim 20, wherein the electronic key circuit comprises a voltagedetection circuit coupled to an external input connection to detect anelevated voltage applied to the external input connection.